Jan 27, 2018  Serial in Parallel out shift register Watch more videos at Lecture By: Ms. Gowthami Swarna, Tutorials Point India Private. Second, the output of the preceding flip-flop since we need a serial shift of data to get a serial output. The multiplexers also need a select input so that will be one extra input port. From the above configurations, we finally get a logic circuit for the 4-bit PISO shift register that looks like this.

The operation of SIPO is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel data output. If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0. The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA.

The logic “1” has now moved or been “shifted” one place along the register to the right as it is now at QA. When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the input to FFA has remained constant at logic level “0”. The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic “1” through the register from left to right as follows.

This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name “ shift register”. A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit, connected together in a serial type daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration.

The number of individual data latches required to make up a single Shift Register device is usually determined by the number of bits to be stored. Shift Registers are commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock ( Clk ) signal making them synchronous devices. Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or “RESET” as required. Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register such as: • Serial-in to Serial-out (SISO): The register is loaded with serial data,one bit at a time, and shifted serially out of the register, one bit at a time in either a left or right direction under clock control. • Serial-in to Parallel-out (SIPO): The register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form.

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• Parallel-in to Serial-out (PISO): The parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. • Parallel-in to Parallel-out (PIPO): The parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse. The effect of data movement from left to right through a shift register can be presented graphically as: Fig.1 Serial-in to Serial-out (SISO) Shift Register Let all the flip-flop be initially in the reset condition i.e. Q A = Q B = Q C = Q D = 0. We enter a four bit binary number 1 1 1 1 into the register.

This number should be applied to D in bit, with the LSB bit applied first. The D input of FFA i.e. D A is connected to serial data input D in. Output of FFA i.e.

Q A is connected to the input of the next flip-flop i.e. D B and so on. Block Diagram Fig.2 Operation Before the application of clock signal let all the flip-flop be initially in the reset condition i.e.

Q A = Q B = Q C = Q D = 0 and apply the LSB bit of the number to be entered to D in. So D in=D A=1.