In general a shift register is characterized by the following control and data. Synchronous/asynchronous parallel load; clock enable; serial or parallel output. 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Serial Out. Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock,.

There is no pin for synchronization. The RS-232 serial protocol has a start and stop bit, logic 0 and 1 respectively. An idle channel will have a logic 1. So if the channel goes from idle to active, 0 will be the first thing you see. If you pick up the channel in the middle of transmission you'll end up having to find the pattern of 10 repeating every 10 bits (8-bit data).

I actually don't think anyone does that type of synchronization. From observation of devices that used RS-232 to receive data, I always remember seeing garbage if you hooked it up in the middle of a burst of data. I think most devices need a pause before achieving synchornization.

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